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R1QKA3618CBG Datasheet(PDF) 16 Page - Renesas Technology Corp |
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R1QKA3618CBG Datasheet(HTML) 16 Page - Renesas Technology Corp |
16 / 38 page PAGE : 16 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series Bus Cycle State Diagram Notes: 1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order is always fixed as: xxx…xxx+0, xxx…xxx+1, xxx…xxx+2, xxx…xxx+3. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read takes precedence. 3. State machine control timing sequence is controlled by K. Read Port NOP R Init = 0 Read Double R Count = R Count + 2 Load New Read Address R Count = 0 R Init = 1 Power Up /R = H Write Port NOP /W = H Supply voltage provided Supply voltage provided /R = L Always /R = L & R Count = 4 Increment Read Address by Two*1 R Init = 0 Always R Count = 2 /R = H & R Count = 4 Write Double W Count = W Count + 2 Load New Write Address W Count = 0 /W = L R Init = 0 Always /W = L & W Count = 4 Increment Write Address by Two*1 Always W Count = 2 /W = H & W Count = 4 --- R10DS0161EJ0009 |
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