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R1QKA3618CBG Datasheet(PDF) 14 Page - Renesas Technology Corp

Part # R1QKA3618CBG
Description  36-Mbit QDRII SRAM 4-word Burst
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1QKA3618CBG Datasheet(HTML) 14 Page - Renesas Technology Corp

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PAGE : 14
Rev. 0.09a : 2011.09.14
R1QGA36**CB* / R1QKA36**CB* Series
C(t+4)
/C(t+3)
C(t+3)
/C(t+2)
RL=2.5
/C(t+3)
C(t+3)
/C(t+2)
C(t+2)
RL=2.0
RL*9=1.5
Q(A+3)
Q(A+2)
Q(A+1)
Q(A+0)
Output
data
D(A+3)
D(A+2)
D(A+1)
D(A+0)
Input
data
C(t+3)
/C(t+2)
C(t+2)
/C(t+1)
Input
clock
for Q
/K(t+2)
K(t+2)
/K(t+1)
K(t+1)
Input
clock
Data out
Data in
Standby (Clock stopped)
NOP (No operation)
Read Cycle:
Load address, output
read data on two
consecutive C and /C
rising edges
Write Cycle:
Load address, input write
data on two consecutive
K and /K rising edges
Operation
K Truth Table
Notes:
1. H: high level, L: low level, : don’t care,
: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C
rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising
edges.
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are
registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K =
high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This
condition is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
7. If this signal was low to initiate the previous cycle, this signal becomes a “don’t care” for this
operation; however, it is strongly recommended that this signal be brought high, as shown in
the truth table.
8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE
operations on consecutive K clock rising edges is not permitted. The device will ignore the
second request.
9. RL = Read Latency (unit = cycle).
L*8
D =
or Q = High-Z
H
H
Previous state
Stopped
L*8
H*7
D or Q
/W
/R
K
R10DS0161EJ0009


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