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R1QKA3618CBG Datasheet(PDF) 13 Page - Renesas Technology Corp |
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R1QKA3618CBG Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 38 page  PAGE : 13 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series IIP NOP Command Read (B2) Ra K, /K Status Qa Qb Qb Rc Qc Qc Qd Qd NOP NOP NOP Write (B2) We De De Df Df Dg Dg Dh Dh Wg Write (B2) Qa DQ DQ ODT Disabled Qj Qi Ri Qi Read (B2) Enabled Disabled Enabled ODT on/off Timing Chart for R1QE series (DDR II+, Burst Length=2, Read Latency=2.5 cycle) Read (B2) Read (B2) Read (B2) Rb Rd Wf Wh Rj Read (B2) Write (B2) Write (B2) NOP Command Read (B4) Ra K, /K Status Qa Qa Qa Rc Qc Qc Qc Qc NOP NOP NOP Write (B4) We De De De De Dg Dg Dg Dg Wg Write (B4) Qa DQ DQ ODT Disabled Qi Qi Ri Qi Read (B4) Enabled Disabled Enabled ODT on/off Timing Chart for R1QF series (DDR II+, Burst Length=4, Read Latency=2.5 cycle) - Read (B4) - - - - NOP Command Read (B2) Ra K, /K Status Qa Qb Qb Rc Qc Qc Qd Qd NOP NOP Write (B2) We De De Df Df Dg Dg Dh Dh Wg Write (B2) Qa DQ DQ ODT Disabled Qj Qi Ri Qi Read (B2) Enabled Disabled Enabled ODT on/off Timing Chart for R1QL series (DDR II+, Burst Length=2, Read Latency=2.0 cycle) Read (B2) Read (B2) Read (B2) Rb Rd Wf Wh Rj Read (B2) Write (B2) Write (B2) Qj Read (B2) Rk Qk Qk NOP Command Read (B4) Ra K, /K Status Qa Qa Qa Rc Qc Qc Qc Qc NOP NOP Write (B4) We De De De De Dg Dg Dg Dg Wg Write (B4) Qa DQ DQ ODT Disabled Qi Qi Ri Qi Read (B4) Enabled Disabled Enabled ODT on/off Timing Chart for R1QM series (DDR II+, Burst Length=4, Read Latency=2.0 cycle) - Read (B4) - - - - Qi Read (B4) Rk Qk Qk Notes 1. ODT on/off switching timings are edge aligned with CQ or /CQ. R10DS0161EJ0009 |
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