Electronic Components Datasheet Search |
|
R1QKA3618CBG Datasheet(PDF) 12 Page - Renesas Technology Corp |
|
|
R1QKA3618CBG Datasheet(HTML) 12 Page - Renesas Technology Corp |
12 / 38 page PAGE : 12 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series IIP Thevenin termination Output Buffer SRAM with ODT 2 R THEV 2 R THEV V DDQ Other LSI Input Buffer V SS ZQ V SS RQ ODT pin = Low or Floating ODT pin = High Off: First Read Command + Read Latency - 0.5 cycle On: Last Read Command + Read Latency + BL/2 cycle + 0.5 cycle (See below timing chart) 3 2 Always Off DQ 0 ~DQn in common I/O devices Always Off Always On K, /K Always Off Always On /BW x Always Off ODT On/Off timing ODT pin (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series) Option 2 Notes: 1. Separate I/O devices are R1QD, R1QK, R1QP series. 2. Common I/O devices are R1QE, R1QF, R1QL, R1QM series. 3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2, please contact Renesas sales office. 1 Always On D 0 ~Dn in separate I/O devices Notes Option 1 Pin name R10DS0161EJ0009 |
Similar Part No. - R1QKA3618CBG |
|
Similar Description - R1QKA3618CBG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |