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R1QKA3618CBG Datasheet(PDF) 6 Page - Renesas Technology Corp |
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R1QKA3618CBG Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 38 page  PAGE : 6 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series Notes: 1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C, /C pins. In the series, K and /K are used as the output reference clocks instead of C and /C. Therefore, hereafter, C and /C represent K and /K in this document. Pin Descriptions 1 Notes IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V SS if the JTAG function is not used in the circuit. Input TCK IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. Input TMS TDI DLL/PLL disable: When low, this input causes the DLL/PLL to be bypassed for stable, low frequency operation. Input /DOFF Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for the first and third output data. The rising edge of C is used as the output timing reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain V REF level. Input C, /C (II only) Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain V REF level. Input K, /K Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input /BW x Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. Input /W Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. Input /R Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst-of-four words (two clock periods of bus activity). These inputs are ignored when device is deselected. Input SA Descriptions I/O type Name hinS=11000.1100.1100.1100.1100 ---11000.1100.1100.1100.1100--- 11000.1100.1100.1100.1100--- QDR R10DS0161EJ0009 |
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