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R1QKA3618CBG Datasheet(PDF) 34 Page - Renesas Technology Corp |
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R1QKA3618CBG Datasheet(HTML) 34 Page - Renesas Technology Corp |
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34 / 38 page  PAGE : 34 Rev. 0.09a : 2011.09.14 R1QGA36**CB* / R1QKA36**CB* Series TAP Controller State Diagram Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR 0 0 1 0 1 1 0 1 0 0 1 Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR 0 0 1 0 1 1 0 1 0 0 1 Run Test/Idle 0 10 1 Test Logic Reset 1 1 0 0 11 Common ID Register # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98765 43210 Symbol R R R 0 C M M M A W W 0 1 Q Q Q B O S 00100010 00111 RRR Q 000 0 001 1 010 Q 011 0 1 CQ 00 11 MMM B 01 0 0 01 1 1 10 1 O 11 0 0 A1 0S 10 WW 1 00 10 11 :: Density = 72Mb Density = 36Mb Latency=1.5 (@II), Latency=2.0 (@II+) Latency=2.5 (@II+) Burst Length = 2 word burst Revison 0 II (QDR-II, DDR-II) Revison 1 Revison 2 Revison 3 Start bit (0) - Revision number (31 :29) Type number (28 : 12) x36 36M&72M w/o ODT, 144M,288M 36M&72M w/ ODT 144M&288M w/o ODT, 36M,72M 144M&288M w/ ODT Burst Length = 4 word burst Density = 144Mb Density = 288Mb Common I/O Separate I/O Vendor JEDEC code x18 x9 (11 : 1) II+ (QDR-II+, DDR-II+) DDR QDR with ODT without ODT R10DS0161EJ0009 |
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