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AN82527F8 Datasheet(PDF) 8 Page - Intel Corporation |
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AN82527F8 Datasheet(HTML) 8 Page - Intel Corporation |
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8 / 22 page  82527 AC Characteristics for 816-Bit Multiplexed Intel Modes (Modes 0 1) Conditions VCC e 5V g10% VSS e 0V TA eb40 Cto a125 C CL e 100 pF Symbol Parameter Min Max Conditions 1tXTAL Oscillator Frequency 8 MHz 16 MHz 1tSCLK System Clock Frequency 4 MHz 10 MHz 1tMCLK Memory Clock Frequency 2 MHz 8 MHz tAVLL Address Valid to ALE Low 75 ns tLLAX Address Hold after ALE Low 10 ns tLHLL ALE High Time 30 ns tLLRL ALE Low to RD Low 20 ns tCLLL CS Low to ALE Low 10 ns tQVWH Data Setup to WR High 27 ns tWHQX Input Data Hold after WR High 10 ns tWLWH WR Pulse Width 30 ns tWHLH WR High to Next ALE High 8 ns tWHCH WR High to CS High 0 ns tRLRH RD Pulse Width 40 ns This time is long enough to initiate a double read cycle by loading the High Speed Registers (04H 05H) but is too short to READ from 04H and 05H (See tRLDV) tRLDV RD Low to Data Valid 0 ns 55 ns (Only for Registers 02H 04H 05H) tRLDV1 RD Low Data to Data Valid (for Registers except 02H 04H 05H) for Read Cycle without a Previous Write(1) 15 tMCLK a 100 ns for Read Cycle with a Previous Write(1) 35 tMCLK a 100 ns tRHDZ Data Float after RD High 0 ns 45 ns tCLYV CS Low to READY Setup 32 ns VOL e 10V Condition Load Capacitance on the READY 40 ns VOL e 045V Output 50 pF tWLYZ WR Low to READY Float for a Write Cycle 145 ns if No Previous Write is Pending(2) tWHYZ End of Last Write to READY Float for a Write 2 tMCLK a 100 ns Cycle if a Previous Write Cycle is Active(2) tRLYZ RD Low to READY Float (for registers except 02H 04H 05H) for Read Cycle without a Previous Write(1) 2tMCLK a 100 ns for Read Cycle with a Previous Write(1) 4tMCLK a 100 ns 8 |
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