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AN82527F8 Datasheet(PDF) 20 Page - Intel Corporation |
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AN82527F8 Datasheet(HTML) 20 Page - Intel Corporation |
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20 / 22 page  82527 15 Page 7 tCLLL decreased from 20 ns to 10 ns 16 Page 3 RESET description addition Warm reset (VCC remains valid while RESET is asserted) RESET must be driven to a valid low level for 1 ms minimum Cold reset (VCC is driven to a valid level while RESET is asserted RESET must be driven low for 1 ms minimum measured from a valid VCC level No falling edge on the reset pin is required during a cold reset event 17 Page 2 Figure 2 Pin 7 name changed to (WR WRL )(RW ) from WR (RW ) 18 Page 4 pin description name changed to (WR WRL )(RW ) from WR (RW ) and WR in 8-bit Intel mode and WRL in 16-bit Intel mode replaces the description WR used for Intel modes 19 Page 5 ABSOLUTE MAXIMUM RATINGS addi- tion Laboratory testing shows the 82527 will withstand up to 10 mA for injected current into both RX0 and RX1 pins for a total of 20 days without sustaining permanent damage This high current condition may be the result of shorted signal lines The 82527 will not function properly if the RX0RX1 input voltage exceeds VCC a 05V 20 Page 12 tCHDV decreased from 25 ns to 15 ns 21 Page 14 tELDV decreased from 25 ns to 15 ns 22 Page 7 tAVLL decreased from 20 ns to 75 ns 23 Page 7 tWHQX decreased from 20 ns to 125 ns This is the -003 revision of the 82527 data sheet The following differences exist between the -002 version and the -003 revision 1 The data sheet has been revised to ADVANCE from PRELIMINARY indicating the specifica- tions have been verified through electrical tests 2 ABSOLUTE MAXIMUM RATINGS have been added 3 VIL no longer applies to the AD0–AD7 pins in CPU Interface mode 3 4 VIL1 has been added to specify Input Low Volt- age for AD0 – AD7 pins in CPU Interface mode 3 as b05V minimum and a05V maximum 5 ICC supply current has been reduced to 50 mA from 100 mA 6 Note 2 was added stating during IPD testing all pins are driven to VSS or VCC including RX0 and RX1 7 tAVLL has been decreased to 20 ns from 33 ns 8 tRLDV1 has been decreased to 15 tMCLK a 100 ns from 2 tMCLK a 100 ns for a Read Cycle without a previous Write (Modes 0 1) tRLDV1 has been decreased to 35 tMCLK a 100 ns from 4 tMCLK a 100 ns for a Read Cycle with a previous Write (Modes 0 1) 9 tCLYV has added the condition of VOL e 10V for a 32 ns delay tCLYV is 40 ns for VOL e 045 (Modes 0 1) 10 tWHYZ has been decreased to 2 tMCLK a 100 ns from 2 tMCLK a 145 ns (Modes 0 1) 11 tEHDV has been decreased to 15 tMCLK a 100 ns from 2 tMCLK a 100 ns for a Read Cycle without a previous Write (Mode 2) tEHDV has been decreased to 35 tMCLK a 100 ns from 4 tMCLK a 100 ns for a Read Cycle with a previous Write (Mode 2) 12 tELEL has been decreased to 2 tMCLK from 2tMCLK a 145 ns (Mode 2) 13 tCLDV has been decreased to 55 ns from 65 ns (Mode 3) 14 tCHKH is specified for VIH e 24V decreased from VIH e 30V Note 3 has been added which states an on-chip pullup will drive DSACK0 to approximately 24V An external pullup is re- quired to drive this signal to a higher voltage (Mode 3) 15 tCHAI has been increased to 10 ns from 5 ns tCHAI no longer includes CS High to RW Invalid (Mode 3) 16 tCHRI e 5 ns has been added to specify CS High to RW Invalid (Mode 3) 17 tEHDV has been decreased to 55 ns from 65 ns for Reads of the High Speed Registers (Mode 3) 18 tEHDV has been decreased to 15 tMCLK a 100 ns from 2 tMCLK a 100 ns for a Read Cycle without a previous Write (Mode 3) tEHDV has been decreased to 35 tMCLK a 100 ns from 4 tMCLK a 100 ns for a Read Cycle with a previous Write (Mode 3) 19 The tAVAL specification name has been correct- ed to tAVAV (Mode 3) 20 tCHAI has been increased to 10 ns from 5 ns (Mode 3) 21 The input voltage in the AC Testing Input Dia- gram have been revised to VCC b 05V from 30V (high level) and revised to 01V from 08V (low level) 20 |
Similar Part No. - AN82527F8 |
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Similar Description - AN82527F8 |
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