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AN82527F8 Datasheet(PDF) 15 Page - Intel Corporation |
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AN82527F8 Datasheet(HTML) 15 Page - Intel Corporation |
15 / 22 page 82527 AC Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Conditions VCC e 5V g10% VSS e 0V TA eb40 Cto a125 C CL e 100 pF Symbol Parameter Min Max 1tXTAL Oscillator Frequency 8 MHz 16 MHz 1tSCLK System Clock Frequency 4 MHz 10 MHz 1tMCLK Memory Clock Frequency 2 MHz 8 MHz tEHDV E High to Data Valid out of High Speed 55 ns Register (02H 04H 05H) Read Cycle without Previous Write for 15 tMCLK a 100 ns Low Speed Registers(1) Read Cycle with Previous Write for 35 tMCLK a 100 ns Low Speed Registers(1) tELDH Data Hold after E Low for a Read 5 ns Cycle tELDZ Data Float after E Low 35 ns tELDV Data Hold after E Low for a Write Cycle 15 ns tAVEH Address and RW to E Setup 25 ns tELAV Address and RW Valid after E Falls 15 ns tCVEH CS Valid to E High 0 ns tELCV CS Valid after E Low 0 ns tDVEL Data Setup to E Low 55 ns tEHEL E Active Width 100 ns tAVAV Start of a Write Cycle after a Previous 2 tMCLK Write Access tAVCL Address or RW to CS Low Setup 3 ns tCHAI CS High to Address Invalid 7 ns tCOPD CLKOUT Period (CDV a 1) tOSC(2) tCHCL CLKOUT High Period (CDV a 1) tOSC b 10 (CDV a 1) tOSC a 15 NOTES 1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 tMCLK 2 Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor 15 |
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