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AN82527F8 Datasheet(PDF) 11 Page - Intel Corporation |
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AN82527F8 Datasheet(HTML) 11 Page - Intel Corporation |
11 / 22 page ![]() 82527 AC Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2) Conditions VCC e 5V g10% VSS e 0V TA eb40 Cto a125 C CL e 100 pF Symbol Parameter Min Max 1tXTAL Oscillator Frequency 8 MHz 16 MHz 1tSCLK System Clock Frequency 4 MHz 10 MHz 1tMCLK Memory Clock Frequency 2 MHz 8 MHz tAVSL Address Valid to AS Low 75 ns tSLAX Address Hold after AS Low 10 ns tELDZ Data Float after E Low 0 ns 45 ns tEHDV E High to Data Valid for Registers 02H 0 ns 45 ns 04H 05H for Read Cycle without a Previous Write(1) 15 tMCLK a 100 ns for Read Cycle with a Previous Write 35 tMCLK a 100 ns (for Registers except for 02H 04H 05H) tQVEL Data Setup to E Low 30 ns tELQX Input Data Hold after E Low 20 ns tELDV E Low to Output Data Valid on Port 12 tMCLK 2tMCLK a 500 ns tEHEL E High Time 45 ns tELEL End of Previous Write (Last E Low) to E 2 tMCLK Low for a Write Cycle tSHSL AS High Time 30 ns tRSEH Setup Time of RW to E High 30 ns tSLEH AS Low to E High 20 ns tCLSL CS Low to AS Low 20 ns tELCH E Low to CS High 0 ns tCOPD CLKOUT Period (CDV a 1) tOSC(3) tCHCL CLKOUT High Period (CDV a 1) tOSC b 10 (CDV a 1) tOSC a 15 NOTES 1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 tMCLK 2 Definition of ‘‘Write Cycle with a Previous Write’’ The time between the falling edge of E (for the previous write cycle) and the falling edge of E (for the current write cycle) is less than 2 tMCLK 3 Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor 11 |
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