 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
FDC37C78-HT Datasheet(PDF) 79 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
FDC37C78-HT Datasheet(HTML) 79 Page - Microchip Technology |
|
|
79 / 82 page  79 t3 t1 t2 t4 t5 t6 t7 t8 t9 t9 nDIR nSTEP nDS0-1 nINDEX nRDATA nWDATA nIOW nDS0-1, nMTR0-1 FIGURE 7 - DISK DRIVE TIMING *X specifies one MCLK period and Y specifies one WCLK period. MCLK = Controller Clock to FDC (See Table 6). WCLK = 2 x Data Rate (See Table 6). Parameter min typ max units t1 t2 t3 t4 t5 t6 t7 t8 t9 nDIR Set Up to nSTEP Low nSTEP Active Time Low nDIR Hold Time After nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTR0-1 from End of nIOW X* X* X* X* X* X* ns Y* ns 4 24 96 132 20 2 40 .5 25 |
Similar Part No. - FDC37C78-HT |
|
Similar Description - FDC37C78-HT |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
