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FDC37C78-HT Datasheet(PDF) 67 Page - Microchip Technology |
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FDC37C78-HT Datasheet(HTML) 67 Page - Microchip Technology |
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67 / 82 page  67 CR05 This register can only be accessed in the Configuration Mode and the CSR has been initialized to 05H. The default value after power up is 00H. Table 39 - CR05- Floppy Disk Extended Setup Register BIT NO. BIT NAME DESCRIPTION 0,1 Reserved Read Only. A read returns a 0. 2 FDC DMA Mode 0=(default) Burst mode is enabled for the FDC FIFO execution phase data transfers. 1=Non-Burst mode enabled. The FDRQ and FIRQ pins are strobed once for each byte transferred while the FIFO is enabled. 4,3 DenSel Bit 4 Bit 3 Densel output 0 0 Normal (Default) 0 1 Reserved 1 0 1 1 1 0 5 Swap Drv 0,1 A high level on this bit, swaps drives and motor sel 0 and 1 of the FDC. A low level on this bit does not (Default). 6 EXTx4 External 4 drive support: 0=Internal 2 drive decoder (default). 1=External 4 drive decoder (External 2 to 4 decoder required). 7 Reserved Read Only. A read of this bit returns a 0 CR06 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 06H. The default value of this register after power up is FFH. This register holds the floppy disk drive types for up to four floppy disk drives. CR07 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 07H. The default value of this register after power up is 00H. This register holds the value for the auto power management, polarity of the media ID bits and floppy boot drive information. |
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