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FDC37C78-HT Datasheet(PDF) 66 Page - Microchip Technology |
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FDC37C78-HT Datasheet(HTML) 66 Page - Microchip Technology |
66 / 82 page 66 CR02 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 02H. The default value of this register after power up is 00H. Table 36 - CR02 BIT NO. BIT NAME DESCRIPTION 0:7 Reserved Read Only. A read returns a 0. CR03 This register can only be accessed in the Configuration Mode and the CSR has been initialized to 03H. The default value after power up is 70H. Table 37 - CR03 BIT NO. BIT NAME DESCRIPTION 0 Reserved Reserved - Read as zero 1 Enhanced Floppy Mode 2 Bit 1 Floppy Mode - Refer to the description of the TAPE DRIVE REGISTER (TDR) for more information on these modes. 0 NORMAL Floppy Mode (Default) 1 Enhanced Floppy Mode 2 (OS2) 2 Reserved Reserved - Read as zero 3 Reserved Reserved - Read as zero 4 DRVDEN1 0 DRVDEN 1 output as per DRVDEN table 1 DRVDEN 1 pin is tri-state (default) 5 MFM IDENT is used in conjunction with MFM to define the interface mode of operation. 6 IDENT IDENT 1 1 0 0 MFM 1 0 1 0 MODE AT Mode (Default) Reserved Reserved Reserved 7 Reserved Reserved - Read as zero CR04 This register can only be accessed in the Configuration Mode and the CSR has been initialized to 04H. The default value after power up is 00H. Table 38 - CR04 BIT NO. BIT NAME DESCRIPTION 0:7 Reserved Reserved - Read as zero |
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