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FDC37C78-HT Datasheet(PDF) 6 Page - Microchip Technology |
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FDC37C78-HT Datasheet(HTML) 6 Page - Microchip Technology |
6 / 82 page 6 DESCRIPTION OF PIN FUNCTIONS DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION HOST PROCESSOR INTERFACE 2-5, 8-11 Data Bus 0-7 D0-D7 I/O12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. 46 I/O Read nIOR I This active low signal is issued by the host microprocessor to indicate a read operation. 47 I/O Write nIOW I This active low signal is issued by the host microprocessor to indicate a write operation. 44-42 I/O Address A0-A2 I These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. 48 DMA Request DRQ O12 This active high output is the DMA request for byte transfers of data between the host and the chip. This signal is cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). 1 n DMA Acknowledge nDACK I An active low input acknowledging the request for a DMA transfer of data between the host and the chip. This input enables the DMA read or write internally. 14 Terminal Count TC I This signal indicates to the chip that DMA data transfer is complete. TC is only accepted when nDACK is low. TC is active high. 13 Interrupt Request IRQ O12 The interrupt request from the logical device is output on the IRQ signal. Refer to the configuration registers for more information. 45 Chip Select Input nCS I When enabled, this active low pin serves as an input for an external decoder circuit which is used to qualify address lines above A2. |
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