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AD9288BSTZ-80 Datasheet(PDF) 16 Page - Analog Devices |
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AD9288BSTZ-80 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 24 page  AD9288 Rev. C | Page 16 of 24 EVALUATION BOARD The AD9218/AD9288 customer evaluation board offers an easy way to test the AD9218 or the AD9288. The compatible pinout of the two parts facilitates the use of one PCB for testing either part. The PCB requires power supplies, a clock source, and a filtered analog source for most ADC testing required. POWER CONNECTOR Power is supplied to the board via a detachable 12-lead power strip. The minimum 3 V supplies required to run the board are VDD, VDL, and VDD. To allow the use of the optional amplifier path, ±5 V supplies are required. ANALOG INPUTS Each channel has an independent analog path that uses a wideband transformer to drive the ADC differentially from a single-ended sine source at the input SMAs. The transformer paths can be bypassed to allow the use of a dc-coupled path by using two AD8138 op amps with a simple board modification. The analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing. VOLTAGE REFERENCE The AD9288 has an internal 1.25 V voltage reference; an external reference for each channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at E18 and E19. The evaluation board is shipped configured for internal reference mode. CLOCKING Each channel can be clocked by a common clock input at SMA input ENCODE A/B. The channels can also be clocked independently by a simple board modification. The clock input should be a low jitter sine source for maximum performance. DATA OUTPUTS The data outputs are latched on-board by two 10-bit latches and drive an 8-pin connector which is compatible with the dual- channel FIFO board available from Analog Devices. This board, together with ADC analyzer software, can greatly simplify ADC testing. DATA FORMAT/GAIN The DFS/Gain pin can be biased for desired operation at the DFS jumper located at the S1, S2 jumpers. TIMING Timing on each channel can be controlled if needed on the PCB. Clock signals at the latches or the data ready signals that go to the output 80-pin connector can be inverted if required. Jumpers also allow for biasing of Pins S1 and S2 for power- down and timing alignment control. |
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Similar Description - AD9288BSTZ-80 |
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