AD9288

Rev. C | Page 5 of 24

TIMING DIAGRAMS

SAMPLE N

SAMPLE N + 1

SAMPLE N + 2

SAMPLE N + 3

SAMPLE N + 4

SAMPLE N + 5

DATA N – 4

DATA N – 4

DATA N – 3

DATA N – 2

DATA N – 1

DATA N

DATA N + 1

ENCODE A, B

DATA N – 3

DATA N – 2

DATA N – 1

DATA N

DATA N + 1

1/fs

Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

SAMPLE

N

SAMPLE

N + 1

SAMPLE

N + 2

SAMPLE

N + 3

SAMPLE

N + 4

ENCODE A

ENCODE B

1/fs

DATA N – 7

DATA N – 5

DATA N – 3

DATA N – 1

DATA N + 1

DATA N + 3

DATA N – 8

DATA N – 6

DATA N – 4

DATA N – 2

DATA N

DATA N + 2

Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing