GL822 Product Overview

©2012 Genesys Logic, Inc. - All rights reserved.

Page 5

CHAPTER 4

BLOCK DIAGRAM

Functional Block Diagram

OCCS USB PHY

The USB 2.0 Transceiver Macrocell is the analog circuitry that handles the low level USB protocol and signaling,

and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. On

chip clock source and no need of 12MHz Crystal Clock input.

SIE

The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing

and state machine logic to handle USB packets and transactions.

EPFIFO

Endpoint FIFO includes Control FIFO (FIFO0), Interrupt FIFO (FIFO3), Bulk In/Out FIFO

 Control FIFO

FIFO of control endpoint 0. It is 64-byte FIFO and used for endpoint 0 data transfer.

 Interrupt FIFO

64-byte depth FIFO of endpoint 3 for status interrupt

 Bulk In/Out FIFO It can be in the TX mode or RX mode:

1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.

2. It can be directly accessed by micro-controller