Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

Device

ACK By

Device

Frame 3 Two-Wire Slave Address Byte

Frame 4 Data Byte 1 Read Register

Start By

Master

ACK By

Device

NACK By

Master

(2)

From

Device

1

9

1

9

1

9

1

9

SDA

SCL

0

0

1

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

¼

¼

SDA

(Continued)

SCL

(Continued)

1

0

0

1

1

0

0

(1)

1

0

0

(1)

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

Device

ACK By

Device

1

9

1

Frame 3 Data Byte 1

ACK By

Device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

1

0

0

(1)

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

Stop By

Master

TMP451

www.ti.com

SBOS686 – JUNE 2013

(1) Slave address 1001100 shown.

Figure 16. Two-Wire Timing Diagram for Write Word Format

(1) Slave address 1001100 shown.

(2) Master should leave SDA high to terminate a single-byte read operation.

Figure 17. Two-Wire Timing Diagram for Single-Byte Read Format

HIGH-SPEED MODE

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue a high-

speed mode (Hs-mode) master code (0000 1xxx) as the first byte after a start condition to switch the bus to high-

speed operation. The TMP451 does not acknowledge this byte, but switches the input filters on SDA and SCL

and the output filter on SDA to operate in HS-mode, allowing transfers at up to 2.5 MHz. After the Hs-mode

master code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation.

The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop

condition, the TMP451 switches the input and output filters back to fast mode operation.

Copyright © 2013, Texas Instruments Incorporated

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