6.42

IDT70V35/34S/L

(IDT70V25/24S/L)

High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

14

NOTES:

1. R/

W or CE or UB & LB must be HIGH during all address transitions.

UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.

CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the

CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.

6. Timing depends on which enable signal is asserted last,

CE, R/W, or UB or LB.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load

(Figure 2).

8. If

OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

9. To access SRAM,

R/

W

(2)

OE

ADDRESS

(6)

(4)

(4)

(7)

CE or SEM

5624 drw 09

(9)

CE or SEM

(9)

(7)

(3)

5624 drw 10

ADDRESS

R/

W

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

(9)