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IDT70V25L15PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V25L15PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 25 page  ©2008 Integrated Device Technology, Inc. OCTOBER 2008 DSC-5624/7 1 Functional Block Diagram IDT70V35/34S/L IDT70V25/24S/L HIGH-SPEED 3.3V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ IDT70V35/34 (IDT70V25/24) easily expands data bus width to 36 bits (32 bits) or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/ S = VIH for BUSY output flag on Master M/ S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ BUSY and Interrupt Flag ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, single 3.3V (±0.3V) power supply ◆ ◆ ◆ ◆ ◆ Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24), 86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24) ◆ ◆ ◆ ◆ ◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information NOTES: 1. A12 is a NC for IDT70V34 and for IDT70V24. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. 4. I/O0x - I/O7x for IDT70V25/24. 5. I/O8x - I/O15x for IDT70V25/24. Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access IDT70V35/34 – Commercial: 15/20/25ns (max.) – Industrial: 20ns IDT70V25/24 – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25ns ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V35/34S – IDT70V35/34L Active: 430mW (typ.) Active: 415mW (typ.) Standby: 3.3mW (typ.) Standby: 660 µW (typ.) – IDT70V25/24S – IDT70V25/24L Active: 400mW (typ.) Active: 380mW (typ.) Standby: 3.3mW (typ.) Standby: 660 µW (typ.) I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL BUSYL A12L(1) A0L 5624 drw 01 UBL LBL CEL OEL I/O9L-I/O17L(5) I/O0L-I/O8L(4) CEL OEL R/ WL SEML INTL M/ S R/ WR BUSYR UBR LBR CER OER I/O9R-I/O17R(5) I/O0R-I/O8R(4) A12R(1) A0R R/ WR SEMR INTR CER OER (3) (2,3) (2,3) (3) 13 13 , |
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