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IDT70V25L15PFG Datasheet(PDF) 23 Page - Integrated Device Technology |
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IDT70V25L15PFG Datasheet(HTML) 23 Page - Integrated Device Technology |
23 / 25 page ![]() 6.42 23 IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be accessed atthesametimewiththeonlypossibleconflictarisingfromthesimultaneous writingof,orasimultaneousREAD/WRITEof,anon-semaphorelocation. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non- semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE andSEMpinscontrol on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. SystemswhichcanbestusetheIDT70V35/34(IDT70V25/24)contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systemscanbenefit fromaperformanceincreaseofferedbytheIDT70V35/ 34 (IDT70V25/24)'s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in systemflexibilitybypermittingsharedresourcestobeallocatedinvarying configurations. The IDT70V35/34 (IDT70V25/24) does not use its sema- phore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high- speedsystems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent oftheDual-PortSRAM.Theselatchescanbeusedtopassaflag,ortoken, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken, the left side should succeed in gaining control. The semaphore flags are activeLOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. TheeightsemaphoreflagsresidewithintheIDT70V35/34(IDT70V25/ 24) in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing aLOWinput on the SEMpin(whichactsas a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W)astheywouldbeusedinaccessingastandard staticRAM.Eachoftheflagshasauniqueaddresswhichcanbeaccessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If aLOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphorecannowonlybemodifiedbythesideshowingthezero.When a one is written into the same location from the same side, the flag will be settoaoneforbothsides(unlessasemaphorerequestfromtheotherside is pending) and then can be written to by both sides. The fact that the side whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor communications.(Athoroughdiscussionontheuseofthisfeaturefollows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output registerwhenthatside'ssemaphoreselect( SEM)andoutputenable(OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been usedinstead,systemcontentionproblemscouldhaveoccurredduringthe gap between the read and write cycles. Itisimportanttonotethatafailedsemaphorerequestmustbefollowed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphoreflagwillforceitssideofthesemaphoreflagLOW andtheother side HIGH. This condition will continue until a one is written to the same semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch have been written to a zero in the meantime, the semaphore flag will flip overtotheothersideassoonasaoneiswrittenintothefirstside’srequest latch.Thesecond side’sflagwillnowstay LOWuntilitssemaphorerequest latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that |
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