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IDT70V25L15PFG Datasheet(PDF) 21 Page - Integrated Device Technology |
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IDT70V25L15PFG Datasheet(HTML) 21 Page - Integrated Device Technology |
21 / 25 page ![]() 6.42 21 IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table III — Interrupt Flag(1) NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. A12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE. Left Port Right Port Function R/ WL CEL OEL A12L-A0L (4) INTL R/ WR CER OER A12R-A0R (4) INTR LL X 1FFF(4) XXX X X L(2) Set Right INTR Flag XXX X X X L L 1FFF(4) H(3) Reset Right INTR Flag XXX X L(3) LL X 1FFE(4) XSet Left INTL Flag XL L 1FFE(4) H(2) X X X X X Reset Left INTL Flag 5624 tbl 15 Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A0 - A11. Inputs Outputs Function CEL CER A12L-A0L (4) A12R-A0R BUSYL(1) BUSYR(1) X X NO MATCH HHNormal H X MATCH H H Normal X H MATCH H H Normal LL MATCH Note(2) Note(2) Write Inhibit(3) 5624 tbl 16 Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24). 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables. Functions D0 - D17 Left(2) D0 - D17 Right(2) Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 5624 tbl 17 |
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