6.42

IDT70V35/34S/L

(IDT70V25/24S/L)

High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

18

Timing Waveform of Write with BUSY

Waveform of BUSY Arbitration Cycle Controlled by Address Match

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

5624 drw 14

R/

R/

(2)

(3)

(1)

,

NOTES:

1.

BUSY input (slave) and output (master).

2.

3.

5624 drw 15

ADDRESSES MATCH

(2)

5624 drw 16

ADDRESS "N"

(2)

MATCHING ADDRESS "N"