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IDT70V25L15PFG Datasheet(PDF) 16 Page - Integrated Device Technology |
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IDT70V25L15PFG Datasheet(HTML) 16 Page - Integrated Device Technology |
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16 / 25 page  6.42 IDT70V35/34S/L (IDT70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges 16 5624 drw 13 tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/ W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD(3) tWDD tBAA tDW Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/ S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/ S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34(6) NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. 'X' in part number indicates power rating (S or L). 70V35/34X15 Com'l Ony 70V35/34X20 Com'l & Ind 70V35/34X25 Com'l Only Symbol Parameter Min.Max.Min.Max. Min. Max. Unit BUSY TIMING (M/S = VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable LOW ____ 15 ____ 20 ____ 20 ns tBDC BUSY Dis able Time from Chip Enable HIGH ____ 15 ____ 17 ____ 17 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 18 ____ 30 ____ 30 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ 17 ____ ns BUSY TIMING (M/S = VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ 17 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 30 ____ 45 ____ 50 ns tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 35 ____ 35 ns 5624 tbl 13 |
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