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TPS65320QPWPRQ1 Datasheet(PDF) 26 Page - Texas Instruments |
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TPS65320QPWPRQ1 Datasheet(HTML) 26 Page - Texas Instruments |
26 / 34 page ![]() TPS65320-Q1 SLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Power Dissipation Switch-Mode Power-Supply Losses: The power dissipation losses are applicable for continuous-conduction-mode (CCM) operation PCON = IO 2 × r DS(on) × (VO / VI) (Conduction losses) PSW = ½ × VI × IO × (tr + tf) × fSW (Switching losses) PGate = Vdrive × Qg × ƒsw (Gate drive losses) Where typically: Qg = 1 × 10 –9 (nC) PIC = VI × Iq-normal (Supply losses) PTotal = PCON + PSW + PGate + PLDO + PIC Where: VO = VREG = Output voltage VI = Input voltage IO = Output current tr = FET switching rise time (tr maximum = 20 ns) tf = FET switching fall time (tf maximum = 20 ns) Vdrive = FET gate-drive voltage (typically Vdrive = 6 V) ƒSW = Switching frequency Linear Regulator: PLDO = (Vbuck – VLDO) × IO For a given operating ambient temperature TAmb TJ = TAmb + Rth × PTotal For a given maximum junction temperature TJ-Max = 150°C TAmb-Max = TJ-Max -Rth × PTotal Where: PTotal = Total power dissipation (W) TAmb = Ambient temperature in °C TJ = Junction temperature in °C TAmb-Max = Maximum ambient temperature in °C TJ-Max = Maximum junction temperature in °C Rth = Thermal resistance of package in (°C/W) Other factors NOT included in the foregoing information which affect the overall efficiency and power losses are: • Inductor ac and dc losses • Trace resistance and losses associated with the copper trace routing connection • Schottky diode PCB Layout TI recommends the following guidelines for PCB layout of the TPS65320-Q1 device. Inductor L Use a low-EMI inductor with a ferrite-type shielded core. One can use other types of inductors; however, they must have low-EMI characteristics and be located away from the low-power traces and components in the circuit. 26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS65320-Q1 |
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