R1

R2

310 S

Power Stage

a

b

Vref = 0.8V

COMP

R3

C1

C2

FB1

Error

Amp

x

x

Inside

TPS65320-Q1

+

±

c

SW

x

TPS65320-Q1

www.ti.com

SLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013

Figure 17. Small-Signal Model for Loop Response

Simple Small-Signal Model for Peak-Current Mode Control

Figure 18 describes a simple small-signal model that one can use to understand how to design the frequency

compensation. A voltage-controlled current source (duty cycle modulator) supplying current to the output

capacitor and load resistor can approximate the TPS65320-Q1 power stage. Equation 5 shows the control-to-

output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the

change in switch current divided by the change in COMP pin voltage (node c in Figure 17) is the power-stage

product of the transconductance and the load resistance as shown in Equation 6.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This

variation with the load may seem problematic at first, but the dominant pole moves with the load current (see

Equation 7). The dashed line in the right half of Figure 18 highlights the combined effect. As the load current

decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same

for the varying load conditions, which makes it easier to design the frequency compensation. The type of output

capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation

design. Using high-ESR aluminium electrolytic capacitors may reduce the number of frequency-compensation

components needed to stabilize the overall loop because the phase margin increases from the ESR zero at the

lower frequencies (see Equation 8).

Figure 18. Simple Small-Signal Model and Frequency Response for Peak-Current Mode

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