RT/CLK

10 pF

4 k:

50 :

Ext Clock Source

PLL

TPS65320

x

TPS65320-Q1

SLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013

www.ti.com

the internal 0.5-V voltage source, the CLK pin becomes high-impedance as the PLL starts to lock onto the

external signal. Because there is a PLL on the regulator, the switching frequency can be higher or lower than the

frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then

increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100

microseconds.

When the device transitions from the PLL mode to the resistor mode, the switching frequency slows down from

the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage, and the resistor then sets the switching

frequency. The switching-frequency divisor changes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on

the FB1 pin. The device implements a digital frequency shift to enable synchronizing to an external clock during

normal start-up and fault conditions.

Figure 16. Synchronizing to a System Clock

Enable and Undervoltage Lockout

TPS65320-Q1 enables are high-voltage-tolerant input pins with an internal pulldown circuit. A high input activates

the device and turns the regulators ON.

TPS65320-Q1 has an internal UVLO circuit to shut down the output if the input voltage falls below an internally

fixed UVLO threshold level. This ensures that both regulators are not latched into an unknown state during low-

input-voltage conditions. The regulators power up when the input voltage exceeds the voltage level.

Overvoltage Transient Protection

The TPS65320-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot

when recovering from output fault conditions or strong unload transients on power-supply designs with low-value

output capacitance. For example, with the power-supply output overloaded, the error amplifier compares the

actual output voltage to the internal reference voltage. If the FB1 pin voltage is lower than the internal reference

voltage for a considerable time, the output of the error amplifier responds by clamping the error amplifier output

to a high voltage, thus requesting the maximum output current. On removal of the condition, the regulator output

rises and the error-amplifier output transitions to the steady-state duty cycle. In some applications, the power-

supply output voltage can respond faster than the error-amplifier output can respond; this actuality leads to the

possibility of an output overshoot. The OVTP feature minimizes the output overshoot when using a low-value

output capacitor by implementing a circuit to compare the FB1 pin voltage to the OVTP threshold (which is 109%

of the internal voltage reference). The FB1 pin voltage going higher than the OVTP threshold disables the high-

side MOSFET, preventing current from flowing to the output and minimizing output overshoot. The FB1 voltage

dropping lower than the OVTP threshold allows the high-side MOSFET to turn on at the next clock cycle.

Small-Signal Model for Loop Response

Figure 17 shows an equivalent model for the TPS65320-Q1 control loop which one can model in a circuit-

simulation program to check frequency response and dynamic load response. The error amplifier is a

amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the

frequency-response measurements. Plotting c versus a shows the small signal response of the frequency

compensation. Plotting a versus b shows the small signal response of the overall loop. Check the dynamic loop

time-domain analysis. This equivalent model is only valid for continuous-conduction-mode designs.

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