0

500

1000

1500

2000

2500

10

20

30

40

50

60

Input Voltage (V)

fsw (Max Skip)

fsw (Shift)

C012

I

V

f

f

div

L

dc

outsc

d

SW

ON

in

L

hs

d

f

(I

R

V

V )

f

(shift)

t

(V

I

R

V )

æ

ö æ

ö

´

+

+

=

´

ç

÷ ç

÷

-

´

+

è

ø è

ø

L

dc

out

d

SW

ON

in

L

hs

d

(I

R

V

V )

1

f

(max skip)

t

(V

I

R

V )

æ

ö æ

ö

´

+

+

=

´

ç

÷ ç

÷

-

´

+

è

ø è

ø

TPS65320-Q1

www.ti.com

SLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013

Equation 4 is the maximum switching frequency limit set by the frequency-shift protection. To have adequate

output short-circuit protection at high input voltages, set the switching frequency should be set be less than the

1 to 8 corresponding to the frequency shift.

In Figure 15, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the

output voltage is zero volts, the resistance of the inductor is 0.130

Ω, the FET on-resistance is 0.127 Ω, and the

diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping.

(3)

(4)

where:

Figure 15. Maximum Switching Frequency versus Input Voltage

How to Interface to RT/CLK Pin

One can use the RT/CLK pin to synchronize the regulator to an external system clock. To implement the

synchronization feature, connect a square wave to the RT/CLK pin through the circuit network shown in

Figure 16. The square-wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin

and have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range

is 300 kHz to 2200 kHz. The rising edge of SW is synchronizes with the falling edge of RT/CLK pin signal.

Design the external synchronization circuit n such a way that the device has the default frequency-set resistor

connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommendes using a

frequency-set resistor connected as shown in Figure 16 through a 50-

Ω resistor to ground. The resistor should

set the switching frequency close to the external CLK frequency. TI also recommends ac-coupling the

synchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-k

Ω series resistor. The

series resistor reduces SW jitter in heavy-load applications when synchronizing to an external clock, and in

applications which transition from synchronizing to RT mode. The first time CLK is pulled above the CLK

threshold, the device switches from the RT resistor frequency to PLL mode. Along with the resulting removal of

Copyright © 2012–2013, Texas Instruments Incorporated

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