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TPS65320QPWPRQ1 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS65320QPWPRQ1 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 34 page ![]() TPS65320-Q1 SLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com DETAILED DESCRIPTION The TPS65320-Q1 device is a 40-V, 3.2-A, step-down (buck) converter with a 280-mA LDO linear regulator. These two regulators both have low quiescent consumption during a light load to prolong the battery life. The buck converter improves performance during line and load transients by implementing a constant-frequency and current-mode control which reduces output capacitance, simplifying external frequency-compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output-filter components. One can adjust the switching frequency by using a resistor to ground on the RT/CLK pin. The buck converter has an internal phase-locked loop (PLL) on the RT/CLK pin that synchronizes the power switch turnon to the falling edge of an external system clock. The TPS65320-Q1 reduces the external component count by integrating the boot recharge diode. A capacitor between the BOOT and SW pins supplies the bias voltage for the integrated high-side MOSFET. An undervoltage lockout (UVLO) circuit monitors the boot capacitor voltage and turns the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS65320-Q1 can operate at high duty cycles because of the boot UVLO. One can step the output voltage down to as low as the 0.8-V reference. Soft start is featured to minimize inrush currents or to provide power-supply sequencing during power up. Connect a small- value capacitor to the pin to adjust the soft-start time. One can couple a resistor divider to the pin for critical power-supply sequencing requirements. The LDO regulator only consumes about 40-µA current in light load. The LDO can also track the battery when battery voltage is low (in a cold-crank condition). The input of the LDO has a unique feature; it can auto source the input supply from either the buck output or the battery. If both the buck and LDO are enabled, the device switches the input of the LDO to the output of the buck to reduce heat. With the buck disabled or the buck output voltage out of regulation (VFB1 less than 91% of VREF), the device switches the LDO input automatically to the input voltage. The LDO of the TPS65320-Q1 device has a power-good comparator (nRST) that asserts when the regulated output voltage is less than 91% of the nominal output voltage. Buck Converter Fixed-Frequency PWM Control The TPS65320-Q1 uses an adjustable, fixed-frequency peak current mode control. Use of external resistors on the VFB1 pin compares the output voltage to an internal voltage reference through an error amplifier that drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The device compares the error amplifier output to the high-side power-switch current. When the power switch current reaches the level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. Slope Compensation Output The TPS65320-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range. Pulse-Skip Eco-mode™ Control Scheme The TPS65320-Q1 operates in a pulse-skip mode at light load currents to improve efficiency by reducing switching and gate drive losses. Design of the TPS65320-Q1 is such that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping-current threshold, the device enters pulse-skip mode. This current threshold is the current level corresponding to a nominal COMP voltage, or 720 mV. The current at which entry to the pulse-skip mode occurs depends on switching frequency, inductor choice, output-capacitor selection, and compensation network. When in pulse-skip mode, the device clamps the COMP pin voltage at 720 mV, inhibiting the high-side MOSFET. Further decreases in load current or in output voltage cannot drive the COMP pin below this clamp-voltage level. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS65320-Q1 |
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