1

2

3

4

5

6

7

14

13

12

11

10

9

8

BOOT

VIN

VIN_LDO

LDO_OUT

FB2

nRST

EN2

SW

Exposed

PowerPAD

GND

COMP

FB1

SS

RT/CLK

EN1

TPS65320-Q1

SLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013

www.ti.com

PIN CONFIGURATION

TPS65320-Q1

PWP-14 HTSSOP Package

(Top View)

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

NO.

BOOT

1

O

Boot node for LX

COMP

12

O

Buck error amplifier output to connect external compensation components

Enable and disable input for buck converter (high-voltage tolerant) internally pulls to ground. Pull up

EN1

8

I

externally to enable.

Enable and disable input for LDO (high-voltage tolerant) internally pulls to ground. Pull up externally to

EN2

7

I

enable.

Remote sense input for buck converter, a resistor network connection between this pin and ground and

FB1

11

I

this pin and buck converter output

Remote sense input for LDO regulator, a resistor network connection between this pin and ground and

FB2

5

I

this pin and LDO_OUT

GND

13

–

Ground

LDO_OUT

4

O

Linear regulator output

Active-low, push-pull reset output, asserted high (at the actual LDO output voltage) after the LDO of the

nRST

6

O

device starts regulating

External resistor connected to ground to program the internal oscillator. An alternative option is to feed

RT/CLK

9

I

an external clock to provide a reference for the switching frequency.

SS

10

I

External capacitor to ground to set the soft-start time

SW

14

I

Source node of internal switching FET

VIN

2

–

Input for internal supply and drain-node input for internal high-side MOSFET

VIN_LDO

3

–

Supply for LDO if Buck regulator is in regulation and supplying at least LDO output voltage plus dropout

Exposed

–

–

Electrically connect to ground and solder to the ground plane of the PCB for thermal efficiency.

thermal pad

6

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