AD5320_05 datasheet(14/20 Pages) AD

Part #	AD5320

Description	2.7 V to 5.5 V, 140 關A, Rail-to-Rail Output 12-Bit DAC in an SOT-23

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Manufacturer	AD [Analog Devices]

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AD5320

Rev. C | Page 14 of 20

MICROPROCESSOR INTERFACING

AD5320 TO ADSP-2101/ADSP-2103 INTERFACE

Figure 28 shows a serial interface between the AD5320 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in the serial port (SPORT) transmit alter-

nate framing mode. The ADSP-2101/ADSP-2103 SPORT are

programmed through the SPORT control register and should

be configured as follows: internal clock operation, active low

framing, and 16-bit word length. Transmission is initiated by

writing a word to the Tx register after the SPORT has been

enabled.

AD5320 TO 68HC11/68L11 INTERFACE

Figure 29 shows a serial interface between the AD5320 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5320, while the MOSI output drives

the serial data line of the DAC. The SYNC signal is derived

from a port line (PC7). For correct operation of this interface,

the 68HC11/68L11 should be configured so that the CPOL bit

is a 0 and the CPHA bit is a 1. When data is being transmitted

to the DAC, the SYNC line is taken low (PC7). When the

68HC11/68L11 are configured, data appearing on the MOSI

output is valid on the falling edge of SCK as shown in Figure 29.

Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes

with only eight falling clock edges occurring in the transmit

cycle. Data is transmitted MSB first. In order to load data to the

AD5320, PC7 is left low after the first eight bits are transferred,

and a second serial write operation is performed to the DAC

and PC7 is taken high at the end of this procedure.

DIN

SCLK

SYNC

PC7

SCK

MOSI

68HC11/68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5320*

Figure 29. AD5320 to 68HC11/68L11 Interface

AD5320 TO 80C51/80L51 INTERFACE

Figure 30 shows a serial interface between the AD5320 and the

80C51/80L51 microcontrollers. TXD of the 80C51/80L51 drives

SCLK of the AD5320, while RXD drives the serial data line of

the part. The SYNC signal is again derived from a bit

programmable pin on the port. In this case, port line P3.3 is

used. When data is to be transmitted to the AD5320, P3.3 is

taken low. The 80C51/80L51 transmits data only in 8-bit bytes;

thus only eight falling clock edges occur in the transmit cycle.

To load data to the DAC, P3.3 is left low after the first eight bits

are transmitted, and a second write cycle is initiated to transmit

the second byte of data. P3.3 is taken high following the

completion of this cycle. The 80C51/ 80L51 output the serial

data in a format that has the LSB first. The AD5320 requires its

data with the MSB as the first bit received. The 80C51/80L51

transmit routine should consider this.

DIN

SCLK

SYNC

P3.3

TXD

RXD

80C51/80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5320*

Figure 30. AD5320 to 80C51/80L51 Interface

AD5320 TO MICROWIRE INTERFACE

Figure 31 shows an interface between the AD5320 and any

MICROWIRE-compatible device. Serial data is shifted out on

the falling edge of the serial clock and is clocked into the

AD5320 on the rising edge of the SK.

DIN

SCLK

SYNC

CS

SK

SO

MICROWIRE*

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5320*

Figure 31. AD5320 to MICROWIRE Interface

SCLK

DIN

SYNC

TFS

DT

SCLK

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5320*

Figure 28. AD5320 to ADSP-2101/ADSP-2103 Interface

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