AD5320_05 datasheet(11/20 Pages) AD

Part #	AD5320

Description	2.7 V to 5.5 V, 140 關A, Rail-to-Rail Output 12-Bit DAC in an SOT-23

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AD5320

Rev. C | Page 11 of 20

THEORY OF OPERATION

D/A SECTION

The AD5320 DAC is fabricated on a CMOS process. The

architecture consists of a string DAC followed by an output

buffer amplifier. Because there is no reference input pin, the

power supply (VDD) acts as the reference. Figure 23 shows a

block diagram of the DAC architecture.

VDD

VOUT

GND

RESISTOR

STRING

REF (+)

REF (–)

OUTPUT

AMPLIFIER

DAC REGISTER

Figure 23. DAC Architecture

Since the input coding to the DAC is straight binary, the ideal

output voltage is given by:

⎟

⎠

⎞

⎜

⎝

⎛

×

=

4096

D

V

DD

OUT

where D = decimal equivalent of the binary code that is loaded

to the DAC register; it can range from 0 to 4095.

RESISTOR STRING

The resistor string section is shown in Figure 24. It is simply a

string of resistors, each of value R. The code loaded to the DAC

register determines at which node on the string the voltage is

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

R

TO OUTPUT

AMPLIFIER

Figure 24. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output that gives an output range of 0 V to VDD. It

is capable of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier

can be seen in Figure 11 and Figure 12. The slew rate is 1 V/μs

with a half-scale settling time of 8 μs with the output unloaded.

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