AD5320_05 datasheet(4/20 Pages) AD

Part #	AD5320

Description	2.7 V to 5.5 V, 140 關A, Rail-to-Rail Output 12-Bit DAC in an SOT-23

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Manufacturer	AD [Analog Devices]

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AD5320

Rev. C | Page 4 of 20

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Limit at TMIN, TMAX

Parameter1, 2

VDD = 2.7 V to 3.6 V

VDD = 3.6 V to 5.5 V

Unit

Description

t13

50

33

ns min

SCLK cycle time

t2

13

ns min

SCLK high time

t3

22.5

13

ns min

SCLK low time

t4

0

ns min

SYNC to SCLK rising edge setup time

t5

5

ns min

Data setup time

t6

4.5

ns min

Data hold time

t7

0

ns min

SCLK falling edge to SYNC rising edge

t8

50

33

ns min

Minimum SYNC high time

1 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2 See Figure 2.

3 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

SCLK

DIN

DB15

DB0

t4

t1

t3

t2

t8

t7

t6

t5

SYNC

Figure 2. Serial Write Operation

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