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Z8523020PSG Datasheet(PDF) 6 Page - Zilog, Inc. |
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Z8523020PSG Datasheet(HTML) 6 Page - Zilog, Inc. |
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6 / 118 page  PS005308-0609 Pin Descriptions Z80230/Z85230/L Product Specification 1 Pin Descriptions The Enhanced Serial Communication Controller (ESCC) pins are divided into seven func- tional groups: 1. Address/Data 2. Bus Timing and Reset 3. Device Control 4. Interrupt 5. Serial Data (both channels) 6. Peripheral Control (both channels) 7. Clocks (both channels) Figure 1 on page 2 and Figure 2 on page 2 display the pins in each functional group for both the Z80230 and Z85230/L. The pin functions are unique to each bus interface version in the Address/Data group, Bus Timing and Reset group, and Device Control group. The Address/Data group consists of the bidirectional lines used to transfer data between the CPU and the ESCC (addresses in the Z80230 are latched by AS). The direction of these lines depends on whether the operation is a Read or a Write operation. The Timing and Control groups designate the type of transaction to occur and the timing of the occurrence. The interrupt group provides inputs and outputs for handling and prior- itizing interrupts. The remaining groups are divided into Channel A and Channel B groups for: • Serial Data (Transmit or Receive) • Peripheral Control (such as DMA or modem) • Input and Output Line for the Receive and Transmit Clocks |
Similar Part No. - Z8523020PSG |
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Similar Description - Z8523020PSG |
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