REV. D

AD9057

–9–

The power-down function of the AD9057 can be done through a

board jumper connection. Connect E7 to E9 (5 V to PWRDN) for

power-down operation. For normal operation, connect E8 to E9

(ground to PWRDN).

The encode signal source should be TTL/CMOS compatible and

capable of driving a 50

W termination (R7). The digital outputs

of the AD9057 are buffered through latches on the evaluation

board (U3) and are available for the user at connector Pins 30

to 37. Latch timing is derived from the ADC encode clock and a

digital clocking signal is provided for the board user at connector

Pins 2 and 21.

An on-board reconstruction digital-to-analog converter is

available for quick evaluations of ADC performance using an

oscilloscope or spectrum analyzer. The DAC converts the ADC’s

digital outputs to an analog signal for examination at the DAC

OUT connector. The DAC is clocked at the ADC encode

frequency. The AD9760 is a 10-bit/100 MSPS single 5 V supply

DAC. The reconstruction signal facilitates quick system trouble-

shooting or confirmation of ADC functionality without requiring

external digital memory, timing, or display interfaces. The DAC

can be used for limited dynamic testing, but customers should note

that test results will be based on the combined performance of the

ADC and DAC (the best ADC performance will be recognized

by evaluating the digital outputs of the ADC directly).

ENCODE

PWRDN

D0–D7

1k

BIAS OUT

3k

2.5k

500

AIN

Digital Inputs

Analog Input

Digital Outputs

Bias Output

Figure 6. Equivalent Circuits