 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MT46V32M16P-5BJ Datasheet(PDF) 1 Page - Micron Technology |
|
|
|||||||||||||||||||||||||||||
MT46V32M16P-5BJ Datasheet(HTML) 1 Page - Micron Technology |
|
|
1 / 93 page 512Mb: x4, x8, x16 DDR SDRAM Features PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN 1 ©2000 Micron Technology, Inc. All rights reserved. Double Data Rate (DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks Features •VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)1 • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center- aligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two – one per byte) • Programmable burst lengths: 2, 4, or 8 •Auto refresh – 64ms, 8192-cycle • Longer-lead TSOP for improved reliability (OCPL) • 2.5V I/O (SSTL_2 compatible) • Concurrent auto precharge option is supported • tRAS lockout supported (tRAP = tRCD) Notes: 1. DDR400 devices operating at < DDR333 conditions can use VDD/VDDQ = +2.5V +0.2V. 2. Available only on Revision F. 3. Available only on Revision J. Options Marking • Configuration – 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 – 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 – 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 • Plastic package – 66-pin TSOP TG – 66-pin TSOP (Pb-free) P – 60-ball FBGA (10mm x 12.5mm) FN2 – 60-ball FBGA (10mm x 12.5mm) (Pb-free) BN2 – 60-ball FBGA (8mm x 12.5mm) CV3 – 60-ball FBGA (8mm x 12.5mm) (Pb-free) CY3 • Timing – cycle time – 5ns @ CL = 3 (DDR400) -5B – 6ns @ CL = 2.5 (DDR333) (FBGA only) -62 – 6ns @ CL = 2.5 (DDR333) (TSOP only) -6T2 • Self refresh – Standard None – Low-power self refresh L • Temperature rating – Commercial (0°C to +70°C) None – Industrial (–40°C to +85°C) IT • Revision – x4, x8, x16 :F – x4, x8, x16 :J Table 1: Key Timing Parameters CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3 Speed Grade Clock Rate (MHz) Data-Out Window Access Window DQS–DQ Skew CL = 2 CL = 2.5 CL = 3 -5B 133 167 200 1.6ns ±0.70ns +0.40ns -6 133 167 n/a 2.1ns ±0.70ns +0.40ns 6T 133 167 n/a 2.0ns ±0.70ns +0.45ns -75E/-75Z 133 133 n/a 2.5ns ±0.75ns +0.50ns -75 100 133 n/a 2.5ns ±0.75ns +0.50ns |
Similar Part No. - MT46V32M16P-5BJ |
|
Similar Description - MT46V32M16P-5BJ |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
