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M24C04-FMC5TG Datasheet(PDF) 24 Page - STMicroelectronics |
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M24C04-FMC5TG Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 38 page  DC and AC parameters M24C16, M24C08, M24C04, M24C02, M24C01 24/38 Doc ID 5067 Rev 17 Table 15. AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R, M24Cxx-F) Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13 Symbol Alt. Parameter Min.(1) 1. All values are referred to VIL(max) and VIH(min). Max.(1) Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tQL1QL2 (2) 2. Characterized only, not tested in production. tF SDA (out) fall time 20(3) 3. With CL = 10 pF. 120 ns tXH1XH2 tR Input signal rise time (4) 4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. (4) ns tXL1XL2 tF Input signal fall time (4) (4) ns tDXCX tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX tDH Data out hold time 100 - ns tCLQV (5)(6) 5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5. tAA Clock low to next data valid (access time) 200 900 ns tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tW tWR Write time - 5 ms |
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