UCC28C40, UCC28C41, UCC28C42, UCC28C43, UCC28C44, UCC28C45

UCC38C40, UCC38C41, UCC38C42, UCC38C43, UCC38C44, UCC38C45

SLUS458E -- AUGUST 2001 -- REVISED OCTOBER 2010

5

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pin assignments

COMP: This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is

frequently used as a control port by utilizing a secondary-side error amplifier to send an error signal across the

secondary-primary isolation boundary through an opto-isolator.

CS: The current sense pin is the non-inverting input to the PWM comparator. This is compared to a signal

proportional to the error amplifier output voltage. A voltage ramp can be applied to this pin to run the device with

a voltage mode control configuration.

FB: This pin is the inverting input to the error amplifier. The non-inverting input to the error amplifier is internally

trimmedto2.5 V ±1%.

GND: Ground return pin for the output driver stage and the logic level controller section.

OUT: The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the

UCC38C40, UCC38C42 and UCC38C43 is the same frequency as the oscillator, and can operate near 100%

duty cycle. In the UCC38C41, UCC38C44 and the UCC38C45, the frequency of OUT is one-half that of the

oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%.

RT/CT: Timing resistor and timing capacitor. The timing capacitor should be connected to the device ground

using minimal trace length.

VDD: Power supply pin for the device. This pin should be bypassed with a 0.1-μF capacitor with minimal trace

lengths. Additional capacitance may be needed to provide hold up power to the device during startup.

VREF: 5-V reference. For stability, the reference should be bypassed with a 0.1-μF capacitor to ground using

the minimal trace length possible.