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S29AL008J70BFI020 Datasheet(PDF) 14 Page - SPANSION |
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S29AL008J70BFI020 Datasheet(HTML) 14 Page - SPANSION |
14 / 54 page 14 S29AL008J S29AL008J_00_11 April 12, 2012 Da ta Sh e e t on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 27 for more information. Refer to the AC Read Operations on page 41 for timing specifications and to Figure 17.1 on page 41 for the timing diagram. ICC1 in DC Characteristics on page 39 represents the active current specification for reading array data. 7.3 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word/Byte Configuration on page 13 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word/ Byte Program Command Sequence on page 28 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.2 on page 16 and Table 7.4 on page 17 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The Command Definitions on page 27 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 18 and Autoselect Command Sequence on page 27 for more information. ICC2 in DC Characteristics on page 39 represents the active current specification for the write mode. AC Characteristics on page 41 contains timing specification tables and timing diagrams for write operations. 7.4 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 33 for more information, and to AC Characteristics on page 41 for timing diagrams. 7.5 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 and ICC4 represents the standby current specification shown in the table in DC Characteristics on page 39. |
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