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S29AL008J70BFI020 Datasheet(PDF) 13 Page - SPANSION

Part # S29AL008J70BFI020
Description  8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S29AL008J70BFI020 Datasheet(HTML) 13 Page - SPANSION

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April 12, 2012 S29AL008J_00_11
S29AL008J
13
Data
She e t
7.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic Low = VIL; H = Logic High = VIH; VID = 8.5 V to 12.5 V; X = Don’t Care; AIN = Address In; DOUT = Data Out
Notes
1. Address In = Amax:A0 in WORD mode (BYTE#=VIH), Address In = Amax:A-1 in BYTE mode (BYTE#=VIL). Sector addresses are Amax
to A12 in both WORD mode and BYTE mode.
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See Sector Group
Protection/Unprotection on page 18.
3. If WP# = VIL, the outermost sector remains protected (determined by device configuration). If WP# = VIH, the outermost sector protection
depends on whether the sector was last protected or unprotected using the method described in Section 7.10, Sector Group Protection/
Unprotection on page 18. The WP# contains an internal pull-up; when unconnected, WP is at VIH.
4. DIN or DOUT as required by command sequence, data polling, or sector group protection algorithm.
7.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
Table 7.1 S29AL008J Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
L
L
H
H
X
AIN
DOUT
DOUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write
L
H
L
H
(Note 3)
AIN
(Note 4)
(Note 4)
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
X
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
High-Z
High-Z
High-Z
Sector Group Protect
(2) (3)
LH
L
VID
H
Sector Address,
A6 = L,
A3 = A2 = L,
A1 = H, A0 = L
(Note 4)
XX
Sector Group
Unprotect (2) (3)
LH
L
VID
H
Sector Address,
A6 = H,
A3 = A2 = L,
A1 = H, A0 = L
(Note 4)
XX
Temporary Sector
Group Unprotect
XX
X
VID
HAIN
(Note 4)
(Note 4)
High-Z


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