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S29AL008J70BFI020 Datasheet(PDF) 49 Page - SPANSION |
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S29AL008J70BFI020 Datasheet(HTML) 49 Page - SPANSION |
49 / 54 page April 12, 2012 S29AL008J_00_11 S29AL008J 49 Data She e t 18. Erase and Programming Performance Notes 1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10.1 on page 32 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. 19. TSOP and BGA Pin Capacitance Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 10 s Excludes 00h programming prior to erasure (Note 4) Chip Erase Time 10 s Byte Programming Time 6 150 µs Excludes system level overhead (Note 5) Word Programming Time 6 150 µs Chip Programming Time Byte Mode 6.3 80 s Word Mode 3.2 60 s Parameter Symbol Parameter Description Test Setup Package Typ Max Unit CIN Input Capacitance VIN = 0 TSOP 4 6 pF BGA 4 6 COUT Output Capacitance VOUT = 0 TSOP 4.5 5.5 BGA 4.5 5.5 CIN2 Control Pin Capacitance VIN = 0 TSOP 5 6.5 BGA 5 6.5 CIN3 WP# Pin Capacitance VIN = 0 TSOP 8.5 10 BGA 8.5 10 |
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