UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com

9

Undervoltage Lockout

Two undervoltage lockout comparators have been

incorporated to guarantee that the IC is fully functional

before the output stage is enabled. The positive power

each monitored by separate comparators. Each has built−in

hysteresis to prevent erratic output behavior as their

upper and lower thresholds are 16 V/10 V for the UCX844B,

upper and lower thresholds are 3.6 V/3.4 V. The large

hysteresis and low startup current of the UCX844B makes

it ideally suited in off−line converter applications where

efficient bootstrap startup techniques are required

(Figure 30). The UCX845B is intended for lower voltage

dc−dc converter applications. A 36 V Zener is connected as

protect the IC from excessive voltage that can occur during

system startup. The minimum operating voltage for the

UCX844B is 11 V and 8.2 V for the UCX845B.

Output

These devices contain a single totem pole output stage that

was specifically designed for direct drive of power

MOSFETs. It is capable of up to

±1.0 A peak drive current

and has a typical rise and fall time of 50 ns with a 1.0 nF load.

Additional internal circuitry has been added to keep the

Output in a sinking mode whenever an undervoltage lockout

is active. This characteristic eliminates the need for an

external pulldown resistor.

The SOIC−14 surface mount package provides separate

implementation will significantly reduce the level of

switching transient noise imposed on the control circuitry.

designer added flexibility in tailoring the drive voltage

to this input when driving power MOSFETs in systems

power and control ground connections in a current−sensing

power MOSFET application.

Reference

The 5.0 V bandgap reference is trimmed to

±1.0%

UC384XB. Its primary purpose is to supply charging current

to the oscillator timing capacitor. The reference has

short−circuit protection and is capable of providing in

excess of 20 mA for powering additional control system

circuitry.

Design Considerations

Do not attempt to construct the converter on

wire−wrap or plug−in prototype boards. High frequency

circuit layout techniques are imperative to prevent

pulse−width jitter. This is usually caused by excessive noise

pick−up imposed on the Current Sense or Voltage Feedback

inputs. Noise immunity can be improved by lowering circuit

impedances at these points. The printed circuit layout should

contain a ground plane with low−current signal and

high−current switch and output grounds returning on

separate paths back to the input filter capacitor. Ceramic

bypass capacitors (0.1

This provides a low impedance path for filtering the high

frequency noise. All high current loops should be kept as

short as possible using heavy copper runs to minimize

radiated EMI. The Error Amp compensation circuitry and

the converter output voltage divider should be located close

to the IC and as far as possible from the power switch and

other noise−generating components.

Bias

+

Osc

R

R

R

2R

EA

5(9)

1(1)

2(3)

4(7)

8(14)

Figure 18. External Clock Synchronization

Figure 19. External Duty Cycle Clamp and

Multi−Unit Synchronization

0.01

The diode clamp is required if the Sync amplitude is large enough to cause

External

Sync

Input

47

+

R

R

R

2R

Bias

Osc

EA

5(9)

1(1)

2(3)

4(7)

8(14)

To Additional

UCX84XBs

R

S

Q

8

4

6

5

2

1

C

3

7

5.0k

5.0k

5.0k

MC1455

f

+

1.44

(RA ) 2RB)C

D(max) +

RA

RA ) 2RB