UC3844B, UC3845B, UC2844B, UC2845B

http://onsemi.com

8

Figure 16. Representative Block Diagram

Figure 17. Timing Diagram

Latch “Set"

Input

Output/

Compensation

Current Sense

Input

Latch “Reset"

Input

Output

+

-

Reference

Regulator

UVLO

+

-

UVLO

3.6V

36V

S

R

Q

Internal

Bias

+ 1.0mA

Oscillator

2.5V

R

R

R

2R

Error

Amplifier

Voltage

Feedback

Input

Output/

Compensation

Current Sense

Comparator

1.0V

GND

5(9)

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input

3(5)

Q1

1(1)

2(3)

4(7)

8(14)

= Sink Only Positive True Logic

Pin numbers adjacent to terminals are for the 8-pin dual-in-line package.

Pin numbers in parenthesis are for the D suffix SOIC-14 package.

PWM

Latch

(See

Text)

T