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UCC28C43DGKG4 Datasheet(PDF) 3 Page - Texas Instruments |
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UCC28C43DGKG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 32 page UCC28C40, UCC28C41, UCC28C42, UCC28C43, UCC28C44, UCC28C45 UCC38C40, UCC38C41, UCC38C42, UCC38C43, UCC38C44, UCC38C45 SLUS458E -- AUGUST 2001 -- REVISED OCTOBER 2010 3 www.ti.com electrical characteristics VDD = 15 V (See Note 1), RT =10kΩ,CT =3.3 nF,CVDD =0.1μF and no load on the outputs, TA =--40°C to 105°C for the UCC28C4x and TA =0°Cto70°C for the UCC38C4x, TA =TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reference Section Output voltage, initial accuracy TA =25°CIOUT =1mA 4.9 5.0 5.1 V Line regulation VDD =12Vto 18 V 0.2 20 mV Load regulation 1mA to 20mA 3 25 mV Temperature stability SeeNote2 0.2 0.4 mV/°C Total output variation SeeNote2 4.82 5.18 V Output noise voltage 10 Hz to 10 kHz, TA =25°C, SeeNote2 50 μV Long term stability 1000 hours, TA = 125°C, SeeNote2 5 25 mV Output short circuit –30 –45 –55 mA Oscillator Section Initial accuracy TA =25°C, SeeNote3 50.5 53 55 kHz Voltage stability VDD =12Vto 18 V 0.2% 1.0% Temperature stability TMIN to TMAX,See Note 2 1% 2.5% Amplitude RT/CT Pin peak-to-peak 1.9 V Discharge current TA =25°C, RT/CT = 2 V, See Note 4 7.7 8.4 9.0 mA Discharge current RT/CT = 2 V, See Note 4 7.2 8.4 9.5 mA Error Amplifier Section Feedback input voltage, initial accuracy VCOMP =2.5 V, TA =25°C 2.475 2.500 2.525 V Feedback input voltage, total variation VCOMP =2.5 V, 2.45 2.50 2.55 V Input bias current VFB =5.0 V –0.1 –2.0 μA Open-loop voltage gain (AVOL) VOUT =2Vto4V 65 90 dB Unity gain bandwidth SeeNote2 1.0 1.5 MHz Power supply rejection ratio (PSRR) VDD =12Vto 18 V 60 dB Output sink current VFB =2.7 V, VCOMP =1.1 V 2 14 mA Output source current VFB =2.3 V, VCOMP =5V –0.5 –1.0 mA High-level output voltage (VOH) VFB =2.7 V, RLOAD =15kto GND 5 6.8 V Low-level output voltage (VOL) VFB =2.7 V, RLOAD = 15 k to VREF 0.1 1.1 V Current Sense Section Gain SeeNote5,6 2.85 3.00 3.15 V/V Maximum input signal VFB <2.4 V 0.9 1.0 1.1 V Power supply rejection ratio (PSRR) VDD = 12 V to 18 V, See Note 2, 5 70 dB Input bias current –0.1 –2.0 μA CS to output delay 35 70 ns COMP to CS offset VCS =0V 1.15 V NOTE: 1. Adjust VDD above the start threshold before setting at 15 V. NOTE: 2. Ensured by design. Not production tested. NOTE: 3. Output frequencies of the UCC38C41, UCC38C44 and the UCC38C45 are half the oscillator frequency. NOTE: 4. Oscillator discharge current is measured with RT =10kΩ to VREF. NOTE: 5. Parameter measured at trip point of latch with VFB =0 V. NOTE: 6. Gain is defined as ACS = ΔVCOM ΔVCS ,0V ≼ VCS ≼ 900mV |
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