W9751G6KB-25 datasheet(32/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 32 -

Revision A04

9.2

Clock Enable (CKE) Truth Table for Synchronous Transitions

CURRENT

STATE

2

CKE

COMMAND (N)

3

RAS , CAS , WE, CS

ACTION (N)

3

NOTES

Previous Cycle

1

(N-1)

Current Cycle

1

(N)

Power Down

L

X

Maintain Power Down

11, 13, 15

L

H

DESELECT or NOP

Power Down Exit

4, 8, 11, 13

Self Refresh

L

X

Maintain Power Down

11, 15, 16

L

H

DESELECT or NOP

Self Refresh Exit

4, 5, 9, 16

Bank(s) Active

H

L

DESELECT or NOP

Active Power Down

Entry

4, 8, 10, 11,

13

All Banks Idle

H

L

DESELECT or NOP

Precharge Power Down

Entry

4, 8, 10, 11,

13

H

L

REFRESH

Self Refresh Entry

6, 9, 11, 13

H

Refer to the Command Truth Table

7

Notes:

1.

CKE (N) is the logic state of CKE at clock edge N; CKE (N

–1) was the state of CKE at the previous clock edge.

2.

Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

3.

COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).

4.

All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

5.

On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period.

Read commands may be issued only after tXSRD (200 clocks) is satisfied.

6.

Self Refresh mode can only be entered from the All Banks Idle state.

7.

Must be a legal command as defined in the Command Truth Table.

8.

Valid commands for Power Down Entry and Exit are NOP and DESELECT only.

9.

Valid commands for Self Refresh Exit are NOP and DESELECT only.

10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set

operations or Precharge operations are in progress. See section 8.9

“Power Down Mode” and section 8.3.7/8.3.8 “Self

Refresh Entry Command/Self Refresh Exit Command

” for a detailed list of restrictions.

11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the

valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not

transition from its valid level during the time period of tIS + 2 x tCK + tIH.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

See section 8.2.4.

13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the

refresh requirements outlined in section 8.9.

14. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode.

15.

“X” means “don‟t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven

high or low in Power Down if the ODT function is enabled

(Bit A2 or A6 set to “1” in EMR (1)).

16. VREF must be maintained during Self Refresh operation.

9.3

Data Mask (DM) Truth Table

FUNCTION

DM

DQS

NOTE

Write enable

L

Valid

1

Write inhibit

H

X

1

Note:

1. Used to mask write data, provided coincident with the corresponding data.

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