W9751G6KB-25 datasheet(31/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 31 -

Revision A04

9.

OPERATION MODE

9.1

Command Truth Table

COMMAND

CKE

BA1

BA0

A12

A11

A10

A9-A0

CS

RAS

CAS

WE

NOTES

Current

Cycle

Bank Activate

H

BA

Row Address

L

H

1, 2

Single Bank

Precharge

H

BA

X

L

X

L

H

L

1, 2

Precharge All

Banks

H

X

H

X

L

H

L

1

Write

H

BA

Column

L

Column

L

H

L

1, 2, 3

Write with

Auto-precharge

H

BA

Column

H

Column

L

H

L

1, 2, 3

Read

H

BA

Column

L

Column

L

H

L

H

1, 2, 3

Read with

Auto-precharge

H

BA

Column

H

Column

L

H

L

H

1, 2, 3

(Extended)

Mode Register

Set

H

BA

OP Code

L

1, 2

No Operation

H

X

L

H

1

Device

Deselect

H

X

H

X

1

Refresh

H

X

L

H

1

Self Refresh

Entry

H

L

X

L

H

1, 4

Self Refresh

Exit

L

H

X

H

X

1, 4, 5

L

H

Power Down

Mode Entry

H

L

X

H

X

1, 6

L

H

Power Down

Mode Exit

L

H

X

H

X

1, 6

L

H

Notes:

1. All DDR2 SDRAM commands are defined by states of

CS , RAS , CAS , WE and CKE at the rising edge of the clock.

2. Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.

3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See

“Burst Interrupt” in section 8.5 for details.

4. VREF must be maintained during Self Refresh operation.

5. Self Refresh Exit is asynchronous.

6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the

refresh requirements outlined in section 8.9.

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