W9751G6KB-25 datasheet(30/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 30 -

Revision A04

8.9.1

Power Down Entry

Two types of Power Down Mode can be performed on the device: Precharge Power Down Mode and

Active Power Down Mode.

If power down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if

power down occurs when there is a row active in any bank, this mode is referred to as Active Power

Down. Entering power down deactivates the input and output buffers, excluding CLK, CLK , ODT and

CKE. Also the DLL is disabled upon entering Precharge Power Down or slow exit Active Power Down,

but the DLL is kept enabled during fast exit Active Power Down.

In power down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the

DDR2

SDRAM, and ODT should be in a valid state but all other input signals are “Don‟t Care”. CKE

LOW must be maintained until tCKE has been satisfied. Maximum power down duration is limited by

the refresh requirements of the device, which allows a maximum of 9 x tREFI if maximum posting of

REF is utilized immediately before entering power down. (Example timing waveforms refer to 11.29 to

11.30 Active and Precharged Power Down Mode Entry and Exit diagram in Chapter 11)

8.9.2

Power Down Exit

The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or

Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable

command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH.

Power-down exit latency is defined at AC Characteristics table of this data sheet.

8.10 Input clock frequency change during precharge power down

DDR2 SDRAM input clock frequency can be changed under following condition:

DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic

LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may

change. SDRAM input clock frequency is allowed to change only within minimum and maximum

operating frequency specified for the particular speed grade. During input clock frequency change,

ODT and CKE must be held at stable LOW levels.

Once input clock frequency is changed, stable new clocks must be provided to DRAM before

precharge power down may be exited and DLL must be RESET via MRS command after precharge

power down exit. Depending on new clock frequency an additional MRS or EMRS command may

need to be issued to appropriately set the WR, CL etc

…

During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to

operate with new clock frequency. (Example timing waveform refer to 11.31 Clock frequency change

in precharge Power Down mode diagram in Chapter 11)

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