W9751G6KB-25 datasheet(29/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 29 -

Revision A04

Table 5

– Precharge & Auto-precharge clarifications

From

Command

To Command

Minimum Delay between “From

Command” to “To Command”

Unit

Notes

Read

Precharge (to same Bank as Read)

AL + BL/2 + max(RTP, 2) - 2

clks

1, 2

Precharge All

AL + BL/2 + max(RTP, 2) - 2

clks

1, 2

Read w/AP

Precharge (to same Bank as Read w/AP)

AL + BL/2 + max(RTP, 2) - 2

clks

1, 2

Precharge All

AL + BL/2 + max(RTP, 2) - 2

clks

1, 2

Write

Precharge (to same Bank as Write)

WL + BL/2 + tWR

clks

2

Precharge All

WL + BL/2 + tWR

clks

2

Write w/AP

Precharge (to same Bank as Write w/AP)

WL + BL/2 + WR

clks

2

Precharge All

WL + BL/2 + WR

clks

2

Precharge

Precharge (to same Bank as Precharge)

1

clks

2

Precharge All

1

clks

2

Precharge

All

Precharge

1

clks

2

Precharge All

1

clks

2

Notes:

1. RTP[cycles] = RU{ tRTP[nS] / tCK(avg)[nS] }, where RU stands for round up.

2. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or

precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command

issued to that bank.

8.8

Refresh Operation

DDR2 SDRAM requires a refresh of all rows in any rolling 64 mS interval. The necessary refresh can

be generated in one of two ways: by explicit Auto Refresh commands or by an internally timed Self

Refresh mode. Dividing the number of device rows into the rolling 64 mS interval defines the average

refresh interval, tREFI, which is a guideline to controllers for distributed refresh timing.

When CS , RAS and CAS are held LOW and WE HIGH at the rising edge of the clock, the chip

enters the Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a

minimum of the Precharge time (tRP) before the Refresh command (REF) can be applied. An address

counter, internal to the device, supplies the bank address during the refresh cycle. No control of the

external address bus is required once this cycle has started. (Example timing waveform refer to 11.28

Self Refresh diagram in Chapter 11)

8.9

Power Down Mode

Power-down is synchronously entered when CKE is registered LOW, along with NOP or Deselect

command. CKE is not allowed to go LOW while mode register or extended mode register command

time, or read or write operation is in progress. CKE is allowed to go LOW while any other operation

such as row activation, Precharge or Auto-precharge or Auto Refresh is in progress, but power down

IDD specification will not be applied until finishing those operations.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset

after exiting power-down mode for proper read operation.

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