W9751G6KB-25 datasheet(25/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 25 -

Revision A04

Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is

prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to

two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms

refer to 11.12 and 11.13 Burst read and write interrupt timing diagram in Chapter 11)

Therefore the Burst Stop command is not supported on DDR2 SDRAM devices.

Table 3

– Burst Length and Sequence

Burst Length

Starting Address

(A2 A1 A0)

Sequential Addressing

(decimal)

Interleave Addressing

(decimal)

4

x00

0, 1, 2, 3

x01

1, 2, 3, 0

1, 0, 3, 2

x10

2, 3, 0, 1

x11

3, 0, 1, 2

3, 2, 1, 0

8

000

0, 1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 0, 1, 6, 7, 4, 5

011

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 4, 5, 2, 3, 0, 1

111

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

8.4.3

Burst read mode operation

Burst Read is initiated with a READ command. The address inputs determine the starting column

address for the burst. The delay from the start of the command to when the data from the first cell

appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is

driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst

is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on

the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an

additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set (MRS). The

AL is defined by the Extended Mode Register EMR (1). (Example timing waveforms refer to 11.6 and

11.7 Data output (read) timing and Burst read operation diagram in Chapter 11)

8.4.4

Burst write mode operation

Burst Write is initiated with a WRITE command. The address inputs determine the starting column

address for the burst. Write Latency (WL) is defined by a Read Latency (RL) minus one and is equal

to (AL + CL -1); and is the number of clocks of delay that are required from the time the write

command is registered to the clock edge associated to the first DQS strobe. A data strobe signal

(DQS) should be driven LOW (preamble) nominally half clock prior to the WL. The first data bit of the

burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble.

The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge

during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until

the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional

data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is

complete. The time from the completion of the burst write to bank precharge is the write recovery time

(WR). (Example timing waveforms refer to 11.8 and 11.9 Data input (write) timing and Burst write

operation diagram in Chapter 11)

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