W9751G6KB-25 datasheet(24/87 Pages) WINBOND

Part #	W9751G6KB-25

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W9751G6KB

Publication Release Date: Sep. 03, 2012

- 24 -

Revision A04

CMD

1

2

3

4

5

6

7

8

9

10

11

12

0

-1

CLK /CLK

DQS/DQS

DQ

AL=2

CL=3

WL=RL-1=4

≥ tRCD

RL=AL+CL=5

Dout0

Din0

Active

A-Bank

Read

A-Bank

Write

A-Bank

Din1

Din2

Din3

Dout1

Dout2 Dout3

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]

Figure 14

– Example 1: Read followed by a write to the same bank,

where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4

1

2

3

4

5

6

7

8

9

10

11

12

0

-1

CL=3

WL=RL-1=2

≥ tRCD

RL=AL+CL=3

AL=0

CMD

CLK/CLK

DQ

Dout0

Dout1 Dout2 Dout3

Din0

Din1

Din2

Din3

Write

A-Bank

Read

A-Bank

Active

A-Bank

DQS/DQS

AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]

Figure 15

– Example 2: Read followed by a write to the same bank,

where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4

8.4.2

Burst mode operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or

from memory locations (read cycle). The parameters that define how the burst mode will operate are

burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8

bit burst mode, full interleave address ordering is supported, however, sequential address ordering is

nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].

The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless

burst read or write operations are supported.

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